Okay I'm back. Its been a while since I've had a chance to even look at this. I haven't worked on a project in quite some time. It was rather depressing when I look at what I've worked on recently and I don't really haven't had anything really exciting to brewing. I've been working on more flight simulator items, but the sudden death of my soldering iron slowed that down.
I do have a new project I've just begun. Its a project I've been dreaming about forever (or at least since the 80s). I don't think I was even 10 when I first had the desire to build my own computer. I've played with a few projects over the years, but the ultimate dream has changed with time.
Recently, inspired by a certain google emplyees' MAGIC-1 project www.homebrewcpu.com I've decided to go all in and build my own computer, CPU and all. Ultimately I wanted to build 3 different machines. A relay computer, TI 7400 based system, and a FPGA solution. My goal is to document these well enough that they could be recreated.
I put off the relay computer, because I don't envision it to be the most rewarding of the three. At the size and scale I am envisioning this project I can only see this useful for recursive calculations. That's not something I really do a lot of.
The FPGA I put off because I've never used one before. I've recently started playing with CPLDs, but not yet FPGAs. So I'll save this one for later. I happen to live in the town where digilent is based. I've even met its founder, and eventually I think I'll be using one of their boards for my project.
So that leaves me with the 7400 based system. I've decided not to emulate any CPU but to go my own way. This leaves me with a few obstacles to overcome, lack of a tool chain, or operating system being the primary. But I hope they will in themselves be interesting projects.
I've sent in my first parts order to mouser this week, so the project may begin. I'm still finalizing the specifications, but several sketches have steered me away from a 512bit data bus (maby version 2). The first piece I plan on building is the ALU. It supports not, and, or, xor, add, and subtract.
I've spent a lot of time deciding what kind of adder I will be using. I found I'm not a fan of look-ahead carry units, I really don't want to complicate the design any more than I have to. However I did have one idea I have been playing with (I'll have to do the math to ensure it really speeds things up). I am calling it a parallel ripple adder (I don't know if anyone uses this method but I haven't found anything yet). The idea is to break the adder into smaller pieces, say 8 bits. The first 8 bits are a standard ripple carry adder. The following bytes are calculated twice, one assumes the previous byte carried and the other assumes it did not. The idea I have the normal delay for a carry adder bit it is only 8 bits. Each additional 8 bits would only have 3 gate delay for the true carries to propagate the correct selection (I'm thinking result_with_carry AND carry OR result_without_carry AND noncarry).
The actual ripple carry adder I've decided to go with is Result = ((A XOR Subtract) XOR B) XOR CarryIn, where CarryIn for the first bit is CarryIn OR Subtract. CarryOut = (((A XOR Subtract) XOR B) AND CarryIn) OR (A AND B)
Well that is a rough outline of where I am now. I'll post drawings here as I finish them. But be warned my eaglecadd skills are not the greatest yet.
I do have a new project I've just begun. Its a project I've been dreaming about forever (or at least since the 80s). I don't think I was even 10 when I first had the desire to build my own computer. I've played with a few projects over the years, but the ultimate dream has changed with time.
Recently, inspired by a certain google emplyees' MAGIC-1 project www.homebrewcpu.com I've decided to go all in and build my own computer, CPU and all. Ultimately I wanted to build 3 different machines. A relay computer, TI 7400 based system, and a FPGA solution. My goal is to document these well enough that they could be recreated.
I put off the relay computer, because I don't envision it to be the most rewarding of the three. At the size and scale I am envisioning this project I can only see this useful for recursive calculations. That's not something I really do a lot of.
The FPGA I put off because I've never used one before. I've recently started playing with CPLDs, but not yet FPGAs. So I'll save this one for later. I happen to live in the town where digilent is based. I've even met its founder, and eventually I think I'll be using one of their boards for my project.
So that leaves me with the 7400 based system. I've decided not to emulate any CPU but to go my own way. This leaves me with a few obstacles to overcome, lack of a tool chain, or operating system being the primary. But I hope they will in themselves be interesting projects.
I've sent in my first parts order to mouser this week, so the project may begin. I'm still finalizing the specifications, but several sketches have steered me away from a 512bit data bus (maby version 2). The first piece I plan on building is the ALU. It supports not, and, or, xor, add, and subtract.
I've spent a lot of time deciding what kind of adder I will be using. I found I'm not a fan of look-ahead carry units, I really don't want to complicate the design any more than I have to. However I did have one idea I have been playing with (I'll have to do the math to ensure it really speeds things up). I am calling it a parallel ripple adder (I don't know if anyone uses this method but I haven't found anything yet). The idea is to break the adder into smaller pieces, say 8 bits. The first 8 bits are a standard ripple carry adder. The following bytes are calculated twice, one assumes the previous byte carried and the other assumes it did not. The idea I have the normal delay for a carry adder bit it is only 8 bits. Each additional 8 bits would only have 3 gate delay for the true carries to propagate the correct selection (I'm thinking result_with_carry AND carry OR result_without_carry AND noncarry).
The actual ripple carry adder I've decided to go with is Result = ((A XOR Subtract) XOR B) XOR CarryIn, where CarryIn for the first bit is CarryIn OR Subtract. CarryOut = (((A XOR Subtract) XOR B) AND CarryIn) OR (A AND B)
Well that is a rough outline of where I am now. I'll post drawings here as I finish them. But be warned my eaglecadd skills are not the greatest yet.
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