Friday, May 20, 2011

Preparing for ALU construction

Most of the parts have arrived.   I am close to being able to begin construction on my ALU.  I've received my XOR, OR, AND, and 4 to 1 ICs.    I've got some boards I will do my prototyping on, I've had them for a while aready.  These Boards from sure electronics are my preferred prototyping boards.   They are vectored with support for more than one power buss, and you can solder on ether side of the board (Very convenient if you want to stack boards).   I decided later on in the project that I wanted to socket the ICs (the fact that I went CMOS had something to do with this), so I'm currently waiting on a shipment of sockets.

As I draw closer to my first prototype of the ALU I'm again revisiting the scale of these.  Originally I wanted to do a 32bit data bus.   The math on this just doesn't work on the prototyping boards I want to use.  This would mean 64 Inputs, 32 ANDd, 32, ORed, 32 XORed, and a few combinations that will have to pass between boards, along with the control signals.   I've only got about 128 lines I can pass between these boards, so 16 bit is looking more likely.   I've even considered dropping back to 8. 

Another limiting factor I hadn't planed on was the board size limitation on eagalecad.  Its A bit more spendy that I would like to license, as I am just starting to learn how to use it.    The size limitation has lead to some rather densely populated boards, that become difficult or impossible to route.   I had fantasised about having boards made as this would save lots of labor, and would be reproducible.

I'm planning on finalizing my a few design pieces of the ALU this weekend.   I'm in the process of determining the fewest number of control signals necessary to control it.   That shouldn't take to long, then I'll try look at how many ICs I can comfortably fit on a board and decide 16bit or 8 bit.   I'll probably do 16bit if at all possible.   

The ALU is the only part that really will be affected adversely by the larger bus size.   The sequencer/controller will ultimately end up simpler if the data bus is wide enough I won't need to decode any instructions, rather the instructions can decode themselves.   Thus the state machine can run off an instruction register directly without having to do combinational decoding.  I'm envisioning a single bit in the instructions that repents what the function is being preformed.  So imagine a bit that indicates a task will be sent to the ALU.   That's all the state machine needs to do.   Other bits will tell witch register should jump on the bust to the ALU inputs.   The ALU can look at the bits on the instruction register to figure out what function it is preforming.   And another couple of bits will tell a witch register should store the result.  Instructions that require 2 or 3 cycles can have bits that affect program flow right from the instruction register. 

So that's the plan now.   Make the data bus as big as possible, Optimises the instructions to simplify the sequencer/controller, build it, program it, and enjoy.

Wednesday, May 18, 2011

I'm Back

Okay I'm back.   Its been a while since I've had a chance to even look at this.    I haven't worked on a project in quite some time.   It was rather depressing when I look at what I've worked on recently and I don't really haven't had anything really exciting to brewing.    I've been working on more flight simulator items, but the sudden death of my soldering iron slowed that down.

I do have a new project I've just begun.  Its a project I've been dreaming about forever (or at least since the 80s).  I don't think I was even 10 when I first had the desire to build my own computer.   I've played with a few projects over the years, but the ultimate dream has changed with time.

Recently, inspired by a certain google emplyees' MAGIC-1 project www.homebrewcpu.com I've decided to go all in and build my own computer, CPU and all.  Ultimately I wanted to build 3 different machines.  A relay computer, TI 7400 based system, and a FPGA solution.   My goal is to document these well enough that they could be recreated. 

I put off the relay computer, because I don't envision it to be the most rewarding of the three.  At the size and scale I am envisioning this project I can only see this useful for recursive calculations.   That's not something I really do a lot of.

The FPGA I put off because I've never used one before.   I've recently started playing with CPLDs, but not yet FPGAs.  So I'll save this one for later.   I happen to live in the town where digilent is based.   I've even met its founder, and eventually I think I'll be using one of their boards for my project.

So that leaves me with the 7400 based system.  I've decided not to emulate any CPU but to go my own way.   This leaves me with a few obstacles to overcome, lack of a tool chain, or operating system being the primary.   But I hope they will in themselves be interesting projects.

I've sent in my first parts order to mouser this week, so the project may begin.  I'm still  finalizing the specifications, but several sketches have steered me away from a 512bit data bus (maby version 2).  The first piece I plan on building is the ALU.  It supports not, and, or, xor, add, and subtract. 

I've spent a lot of time deciding what kind of adder I will be using.  I found I'm not a fan of look-ahead carry units, I really don't want to complicate the design any more than I have to.  However I did have one idea I have been playing with (I'll have to do the math to ensure it really speeds things up).   I am calling it a parallel ripple adder (I don't know if anyone uses this method but I haven't found anything yet).  The idea is to break the adder into smaller pieces, say 8 bits.    The first 8 bits are a standard ripple carry adder.  The following bytes are calculated twice, one assumes the previous byte carried and the other assumes it did not.  The idea I have the normal delay for a carry adder bit it is only 8 bits.    Each additional 8 bits would only have 3 gate delay for the true carries to propagate the correct selection (I'm thinking result_with_carry AND carry OR result_without_carry AND noncarry).

The actual ripple carry adder I've decided to go with is Result = ((A XOR Subtract) XOR B) XOR CarryIn, where CarryIn for the first bit is CarryIn OR Subtract.   CarryOut = (((A XOR Subtract) XOR B) AND CarryIn) OR (A AND B)

Well that is a rough outline of where I am now.  I'll post drawings here as I finish them.   But be warned my eaglecadd skills are not the greatest yet.